verilog编程显示“Can't elaborate user hierarchy”怎么办

问题描述

精选答案

因为同时检测两个信号的状态，会导致发生错误。

以下是正确代码:

reg [ 25:0 ] count_del ;

always @ ( posedge clk or negedge rst_n )

if(!rst_n )

count_del

else if ( key_out )

count_del

else if(count_del==26'd50000001)

count_del

else count_del